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Man Pages

Manual Reference Pages  - PCI (9)


pci, pci_read_config, pci_write_config, pci_enable_busmaster, pci_disable_busmaster, pci_enable_io, pci_disable_io, pci_set_powerstate, pci_get_powerstate, pci_find_bsf, pci_find_device - PCI bus interface


Implementation Notes
See Also


.In sys/bus.h
.In dev/pci/pcivar.h
.In dev/pci/pcireg.h
.In machine/pci_cfgreg.h void pci_write_config device_t dev int reg uint32_t val int width int pci_enable_busmaster device_t dev int pci_disable_busmaster device_t dev int pci_enable_io device_t dev int space int pci_disable_io device_t dev int space int pci_set_powerstate device_t dev int state int pci_get_powerstate device_t dev uint32_t pci_read_config device_t dev int reg int width device_t pci_find_bsf uint8_t bus uint8_t slot uint8_t func device_t pci_find_device uint16_t vendor uint16_t device


The pci set of functions are used for managing PCI devices.

The pci_read_config function is used to read data from the PCI configuration space of the device dev, at offset reg, with width specifying the size of the access.

The pci_write_config function is used to write the value val to the PCI configuration space of the device dev, at offset reg, with width specifying the size of the access.

The pci_enable_busmaster function enables PCI bus mastering for the device dev, by setting the PCIM_CMD_BUSMASTEREN bit in the PCIR_COMMAND register. The pci_disable_busmaster function clears this bit.

The pci_enable_io function enables memory or I/O port address decoding for the device dev, by setting the PCIM_CMD_MEMEN or PCIM_CMD_PORTEN bit in the PCIR_COMMAND register appropriately. The pci_disable_io function clears the appropriate bit. The space argument specifies which resource is affected; this can be either SYS_RES_MEMORY or SYS_RES_IOPORT as appropriate.

NOTE: These functions should be used in preference to manually manipulating the configuration space.

The pci_get_powerstate function returns the current ACPI power state of the device dev. If the device does not support power management capabilities, then the default state of PCI_POWERSTATE_D0 is returned. The following power states are defined by ACPI:
PCI_POWERSTATE_D0 State in which device is on and running. It is receiving full power from the system and delivering full functionality to the user.
PCI_POWERSTATE_D1 Class-specific low-power state in which device context may or may not be lot. Busses in this state cannot do anything to the bus, to force devices to lose context.
PCI_POWERSTATE_D2 Class-specific low-power state in which device context may or may not be lost. Attains greater power savings than PCI_POWERSTATE_D1. Busses in this state can cause devices to lose some context. Devices must be prepared for the bus to be in this state or higher.
PCI_POWERSTATE_D3 State in which the device is off and not running. Device context is lost, and power from the device can be removed.
  State of the device is unknown.

The pci_set_powerstate function is used to transition the device dev to the ACPI power state state. It checks to see if the device is PCI 2.2 compliant. If so, it checks the capabilities pointer to determine which power states the device supports. If the device does not have power management capabilities, the default state of PCI_POWERSTATE_D0 is set.

The pci_find_bsf function looks up the
.Vt device_t of a PCI device, given its bus, slot, and func. The slot number actually refers to the number of the device on the bus, which does not necessarily indicate its geographic location in terms of a physical slot.

The pci_find_device function looks up the
.Vt device_t of a PCI device, given its vendor and device IDs. Note that there can be multiple matches for this search; this function only returns the first matching device.


.Vt pci_addr_t type varies according to the size of the PCI bus address space on the target architecture.


pci(4), pciconf(8), bus_alloc_resource(9), bus_dma(9), bus_release_resource(9), bus_setup_intr(9), bus_teardown_intr(9), devclass(9), device(9), driver(9), rman(9)
.Rs NewBus


This manual page was written by
.An Bruce M Simpson Aq .


The kernel PCI code has a number of references to "slot numbers". These do not refer to the geographic location of PCI devices, but to the device number assigned by the combination of the PCI IDSEL mechanism and the platform firmware. This should be taken note of when working with the kernel PCI code.
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January 22, 2005 PCI (9)

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