NAME

SYNOPSIS

DESCRIPTION

On the first write to the character device at file offset 0, the devcfg driver asserts the top-level PL reset signals, disables the PS-PL level shifters, and clears the PL configuration. Write data is sent to the PCAP (processor configuration access port). When the PL asserts the DONE signal, the devcfg driver will enable the level shifters and release the top-level PL reset signals.

The PL (FPGA) can be configured by writing the bitstream to the character device like this:

cat design.bit.bin > /dev/devcfg

The file should not be confused with the .bit file output by the FPGA design tools. It is the binary form of the configuration bitstream. The Xilinx promgen tool can do the conversion:

promgen -b -w -p bin -data_width 32 -u 0 design.bit -o design.bit.bin

SYSCTL VARIABLES

hw.fpga.pl_done

This variable always reflects the status of the PL's DONE signal. A 1 means the PL section has been properly programmed.

hw.fpga.en_level_shifters

This variable controls if the PS-PL level shifters are enabled after the PL section has been reconfigured. This variable is 1 by default but setting it to 0 allows the PL section to be programmed with configurations that do not interface to the PS section of the part. Changing this value has no effect on the level shifters until the next device reconfiguration.

FILES

/dev/devcfg

Character device for the devcfg driver.

SEE ALSO

AUTHORS