Types

For example, the function to atomically add two integers is called atomic_add_int().

Certain architectures also provide operations for types smaller than “int”.

These types must not be used in machine-independent code.

Acquire and Release Operations

Atomic operations on memory have up to three variants. The first, or relaxed variant, performs the operation without imposing any ordering constraints on accesses to other memory locations. This variant is the default. The second variant has acquire semantics, and the third variant has release semantics.

When an atomic operation has acquire semantics, the operation must have completed before any subsequent load or store (by program order) is performed. Conversely, acquire semantics do not require that prior loads or stores have completed before the atomic operation is performed. An atomic operation can only have acquire semantics if it performs a load from memory. To denote acquire semantics, the suffix “_acq” is inserted into the function name immediately prior to the “_⟨type⟩” suffix. For example, to subtract two integers ensuring that the subtraction is completed before any subsequent loads and stores are performed, use atomic_subtract_acq_int().

When an atomic operation has release semantics, all prior loads or stores (by program order) must have completed before the operation is performed. Conversely, release semantics do not require that the atomic operation must have completed before any subsequent load or store is performed. An atomic operation can only have release semantics if it performs a store to memory. To denote release semantics, the suffix “_rel” is inserted into the function name immediately prior to the “_⟨type⟩” suffix. For example, to add two long integers ensuring that all prior loads and stores are completed before the addition is performed, use atomic_add_rel_long().

When a release operation by one thread synchronizes with an acquire operation by another thread, usually meaning that the acquire operation reads the value written by the release operation, then the effects of all prior stores by the releasing thread must become visible to subsequent loads by the acquiring thread. Moreover, the effects of all stores (by other threads) that were visible to the releasing thread must also become visible to the acquiring thread. These rules only apply to the synchronizing threads. Other threads might observe these stores in a different order.

In effect, atomic operations with acquire and release semantics establish one-way barriers to reordering that enable the implementations of synchronization primitives to express their ordering requirements without also imposing unnecessary ordering. For example, for a critical section guarded by a mutex, an acquire operation when the mutex is locked and a release operation when the mutex is unlocked will prevent any loads or stores from moving outside of the critical section. However, they will not prevent the compiler or processor from moving loads or stores into the critical section, which does not violate the semantics of a mutex.

Thread Fence Operations

When a fence has acquire semantics, all prior loads (by program order) must have completed before any subsequent load or store is performed. Thus, an acquire fence is a two-way barrier for load operations. To denote acquire semantics, the suffix “_acq” is appended to the function name, for example, atomic_thread_fence_acq().

When a fence has release semantics, all prior loads or stores (by program order) must have completed before any subsequent store operation is performed. Thus, a release fence is a two-way barrier for store operations. To denote release semantics, the suffix “_rel” is appended to the function name, for example, atomic_thread_fence_rel().

Although atomic_thread_fence_acq_rel() implements both acquire and release semantics, it is not a full barrier. For example, a store prior to the fence (in program order) may be completed after a load subsequent to the fence. In contrast, atomic_thread_fence_seq_cst() implements a full barrier. Neither loads nor stores may cross this barrier in either direction.

In C11, a release fence by one thread synchronizes with an acquire fence by another thread when an atomic load that is prior to the acquire fence (by program order) reads the value written by an atomic store that is subsequent to the release fence. In constrast, in FreeBSD, because of the atomicity of ordinary, naturally aligned loads and stores, fences can also be synchronized by ordinary loads and stores. This simplifies the implementation and use of some synchronization primitives in FreeBSD.

Since neither a compiler nor a processor can foresee which (atomic) load will read the value written by an (atomic) store, the ordering constraints imposed by fences must be more restrictive than acquire loads and release stores. Essentially, this is why fences are two-way barriers.

Although fences impose more restrictive ordering than acquire loads and release stores, by separating access from ordering, they can sometimes facilitate more efficient implementations of synchronization primitives. For example, they can be used to avoid executing a memory barrier until a memory access shows that some condition is satisfied.

Interrupt Fence Operations

Multiple Processors

Semantics

atomic_add(p, v)

*p += v;
    

atomic_clear(p, v)

*p &= ~v;
    

atomic_cmpset(dst, old, new)

if (*dst == old) {
	*dst = new;
	return (1);
} else
	return (0);
    

Some architectures do not implement the atomic_cmpset() functions for the types “char”, “short”, “8”, and “16”.

atomic_fcmpset(dst, *old, new)

On architectures implementing Compare And Swap operation in hardware, the functionality can be described as

if (*dst == *old) {
	*dst = new;
	return (1);
} else {
	*old = *dst;
	return (0);
}

Some architectures do not implement the atomic_fcmpset() functions for the types “char”, “short”, “8”, and “16”.

atomic_fetchadd(p, v)

tmp = *p;
*p += v;
return (tmp);
    

The atomic_fetchadd() functions are only implemented for the types “int”, “long” and “32” and do not have any variants with memory barriers at this time.

atomic_load(p)

return (*p);
    

atomic_readandclear(p)

tmp = *p;
*p = 0;
return (tmp);
    

The atomic_readandclear() functions are not implemented for the types “char”, “short”, “ptr”, “8”, and “16” and do not have any variants with memory barriers at this time.

atomic_set(p, v)

*p |= v;
    

atomic_subtract(p, v)

*p -= v;
    

atomic_store(p, v)

*p = v;
    

atomic_swap(p, v)

tmp = *p;
*p = v;
return (tmp);
    

The atomic_swap() functions are not implemented for the types “char”, “short”, “ptr”, “8”, and “16” and do not have any variants with memory barriers at this time.

atomic_testandclear(p, v)

bit = 1 << (v % (sizeof(*p) * NBBY));
tmp = (*p & bit) != 0;
*p &= ~bit;
return (tmp);
    

atomic_testandset(p, v)

bit = 1 << (v % (sizeof(*p) * NBBY));
tmp = (*p & bit) != 0;
*p |= bit;
return (tmp);
    

The atomic_testandset() and atomic_testandclear() functions are only implemented for the types “int”, “long” and “32” and do not have any variants with memory barriers at this time.

The type “64” is currently not implemented for some of the atomic operations on the arm, i386, and powerpc architectures.